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- Buffer circuits for digital CMOS
- Linear x10 Amplifier by 4011 Gate
- 1 Hz Timebase circuit using IC-4017
- Two divide counter circuit using IC-4027
- A diode protect CMOS circuit
- Level Voltage of Logic Changer using JFET
- Pulse delayer circuit using CD4528
- 7 Stage Binary Counter Display with LED using CD4024
- 4511 Binary to Decimal decoder
- Counter Display with LED 7 Segment Using CMOS
- 0-99 Two Digit Counter By IC 74LS48 , 74LS90
- LED display with NAND gate digital control
- Rising-edge trigger R-S Flip Flop circuit
Buffer circuits for digital CMOS
If you want the circuit Output buffer for the circuit digital. I suggest the IC-4050 (Hex buffers with high-to-low level shifter inputs) because very be IC that be usable easily. use link up digital circuit TTL and CMOS well.
The family of CMOS digital ICs has many strengths. It can be used to power a 3-16V, Easy and cheap. It has the same frequency is not high. A slow response that IC – TTL applications are easy to use and cheap. Slow response to IC – TTL applications. The problem that I found as the current is low. Do not apply to other circuits or the load current is greater than 50mA. However, we have several ways to increase the buffer circuit such as the transistor and a buffer circuit. This circuit continues on this issue, we use the IC 4050 is characterized by several parallel butter gate. However, we have several ways to increase the buffer circuit. Maybe uses a transistor and a buffer IC circuit.
In this circuit, the answer to this problem, we use the IC 4050 is characterized by several parallel butter gate. Normally single gate circuit can supply up to about 15mA. When we put the gate parallel together will help Increases the current very well. The circuit is in highly stable up.
Linear x10 Amplifier by 4011 Gate
This is very basic amplifier circuit,so I use IC digital Cmos 4011 quad NAND gate.
It is to give equal to 10x linear amplifier.
The resistor R1 = 1M ohm , R2 = 10M ohm.
This circuit can not output speaker because it is very low power amplifier.
1 Hz Timebase circuit using IC-4017
I used input frequency 10Hz to output 1Hz.This is a 10 divider circuit.
When we need a standard digital clock 1 Hz. but we have the input signal is square wave form 10 Hz so need to reduct it lower with digital frequency divider circuit 10 times
I suggest that IC 4017 (Decade Counter / Divider with 10 Decoded) from the familiar to make a 10 LEDs running light circuits, but this circuit we used a frequency dividing circuit 10 times, too.
It’s interesting because it uses a single IC run it. The circuit is very simple. Would not be very descriptive. Enjoy it.
Two divide counter circuit using IC-4027
When you want to decrease the frequency in 2 digital times circuits or Divide Frequency by 2 counter. I advises use IC 4017, because seek easy cheapness can be usable good various.
A diode protect CMOS circuit
The CMOS digital circuit used to produce an oscillator, with pulse low-frequency form. We use R and C are a lot of period of time. it must have a diode to prevent current flow feedback.
In the oscillator circuit, we use the CD40106 and 74HCT132.The D1 and D2 connected to the input terminal of the twin IC respectively. These diodes should be outside the IC, because if the diode within the IC. When too much current flow will cause the loss diode and IC too.
Level Voltage of Logic Changer using JFET
This is a logic signal changer circuit, the normal voltage of about 5V. But sometimes we want to 12V or 15V, we can use a JFET. It works by mode COMMON GATE.
The simple principle is that when a logic “0” or 0V. The JFET N-channel type which will stop the conduction, The voltage between D and G was 0V too. And if logic “1” with the voltage 5V, N-channel conduction.
The voltage between pins D and G is equal to VS, which may be equal to any 12 Volt or 15 volts.
The R1 will determine the speed and power loss of the circuit, the resistance R1 is in the range of 100K to 1M, so the current flowing through it is in the 150uA to 15uA.We can also determine the frequency of the pulse matches with. The limit of approximately 1 MHz.
A key advantage of this circuit is, can be applied to the device driver voltage is higher than 5 volt.
Pulse delayer circuit using CD4528
The Pulse delayer circuit this use IC 4528 help delay pulse or oscillator the all. For a signal is a pulse that postpones long ago go up. By fix give R1 control while delay, R2 control the wideness of pulse to delay. The detail is other see in circuit picture.
7 Stage Binary Counter Display with LED using CD4024
This circuit basically the base of the usability IC number CD4042 (7 Stage binary counter). By the circuit will regard the binary digit arrive at 128 BIT. Then show with LED 7 the make easy build the education.
When feed power supply give with the circuit IC1 as a result will change way position output every time. When receive pulse signal from pressure switch S1. By pin 1 (CK) will receive pulse signal pin edge goes up to are logic “1” and when liberate switch receive signal pin edge down is logic “0” thus when press switch S1 time that 2 LED2 stick bright. But LED1 switch off which be the show output the two base is 001 and when press switch S1 time that 3 LED1 and LED2 stick bright. But LED3 switch off display be output the base is two be 011. when press switch time build go to as a result will display be the binary digit goes to continually until arrive in time that 129 which LED1-LED7 will stick bright and the integrated circuit will do something reset begin count at new zero output every a leg has will logic “0” cause LED1-LED7 switch off be finished every.
4511 Binary to Decimal decoder
Counter Display with LED 7 Segment Using CMOS
This is the simple digital counter circuit, the IC application number 4029 from binary data, and then sent to the IC number 4513, a driver IC 7 Segment, to show off a digital number from 0 to 9.
When entering into a pulse signal input pin 15 of IC1, it will signal to the output signal is Binary.Then send the output from the pin Q0, Q1, Q2, Q3, and the pin. 6, 11, 14 and 2 of IC1.Go to the input of IC2 No. 4513. Which is IC displayed by the decoder signal to the Binary LED display with a 7 or the 7 Segment, will be displayed from a digital number from 0-9.
0-99 Two Digit Counter By IC 74LS48 , 74LS90
This is circuit 0-99 Two Digital Counter.
use IC TTL Digital IC 74LS48 x 2 to LED 7 segment Display,
and 74LS90 x 2 for Decade and Binary Counters.
Input Clock pin 14 from IC 74LS90.
Here is circuit use power supply 5V.
LED display with NAND gate digital control
This circuit operates in the digital circuit.It has 2 inputs are inputs inputs A and B inputs to receive input, By used nand gate ICs,To control the on-off of the lamp.
Operation of the circuit. When the input to the A is listed as “0” or “1”.And B is listed as “0” will cause the output of IC1 / 3 to “0”.The Q1 does not work will not light LED1.But if the A is listed as “0” and B is listed as “1” will cause the output of IC1 / 3 to “1” As a result, Q1 LED1 light work.
But if the A is listed as “1” and B is listed as “1” will enable LED1 blinking frequency of approximately 3.5 Hz.The principle is working. The first two legs of the conditions IC1 / 1 “0” to the output Into “1”.And IC1 / 2 off the output is “0” IC1 / 3 to return to the status output from a “1” LED1 is light.And caused a charge of C1.This will take and when will fully charge C1 pin 2 of IC1 / 1 is “1” makes the output from “0”.And IC1 / 2 off the output is “1” and IC1 / 3 to return to the status output from a “0” LED1 is extinguished. And caused the discharge of C1 through the voltage of R2 through the voltage of C1 gradually decreased.The voltage at pin 2 of IC1 / 1 to 0 volts of this work will continue, causing LED1 flashes.
Rising-edge trigger R-S Flip Flop circuit
The normal R-S flip flop circuit include of two nade gate are connected together and when need to set or reset then feed the logic signal is “1” instead trigger and use inverter work instead.
In Figure 1 suppose begin state of both input is “0” and output Q is “1”, input of N1 will be pulled to “1” by the 180 K resistors. Thus output Q so is “0”, that input of N2 is also “0”. Then if feed logic “1” to input s output -Q will be “0” pull input of N1 is also “0” and output Q will be “1”.
Thus input of N2 will be pulled as “1” Although input S is “0” another matter. And When feed logic “1” into the input R will reset the flip flop and Process change would be opposite to the above.
The R-S flip flop circuit should drive easily the load that has resistance of 180K at logic “1”. The CMOS circuit can drive the load on this already.
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