CD4027 datasheet of Dual J-K Flip-Flop

This is the CD4027 datasheet of dual J-K flip-flops are monolithic complementary MOS (CMOS) integrated circuits. Its internal structure consists of N- and P-channel enhancement mode transistors.

Each flip-flop has independent J, K, set, reset, and clock inputs and buffered Q and Q outputs.

These flip-flops are edge sensitive to the clock input and change state on the positive -going transition of the clock pulses.

cd4027 connection diagrams
The connection diagram

Set or reset is independent of the clock and is accomplished by a high level of the respective input.

The diode clamps across VDD and VSS to protect against damage to All inputs, due to static discharge.


– Wide supply voltage range: 3.0V to 15V
– High noise immunity: 0.45 V(typ.)
– Low power TTL compatibility: Fan out of 2 driving 74L or 1 driving 74LS
– Low power: 50 nW (typ.)
– Medium speed operation: 12 MHz (typ.) with 10V

The truth table

Also CD4027 Circuits

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