System designers must consider the timing and voltage differences between core and I/O power supplies (in other words, power-supply sequencing) during power-up and power-down. The possibility of a latch-up failure or excessive current draw exists when power-supply sequencing does not occur properly. The trigger for latch-up may occur if power supplies apply different potentials to the core and …..
Read More Source:
http://www.reed-electronics.com/ednmag/
index.asp?layout=article&articleId=CA269853
Thank you.
This entry was posted on Wednesday, April 16th, 2008 at 7:51 am and is filed under Electronic Control, motor speed controller.
