CD4046 datasheet (phase-locked loop)

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  Posted by admin - July 11, 2013 at 2:52 am

The CD4046 is Phase-locked loop IC of CMOS digital (combined analog and digital chip).

A Phase-locked loop(PLL) has a voltage-controlled oscillator(VCO).

The VCO signal and an input signal are sent vto a phase comparator which generates an error voltage part to any difference in frequency between two signals.

The error voltage adjusts the VCO frequency to match that of the input signal.

Thus the PLL can track an input signal.

Or only the VCO function can be used.

The specifications and CMOS IC use and handling caution.

block-connection-diagrams
In the Figure 1 is a block diagram connections of CD4046

The supply voltage Range: +3 volts to +18 volts VCO frequency linearity: 1% typical.

It is a cmos chip that requires special practice.

There’s much more about cmos in your digital logic workbook.

The follow these guidelines for use.

1. Connect unused inputs (pins 3,5,9 and 14) to ground or the positive supply voltage.

2. Pins 6,7,10,11,12 and 15 should be lift disconnected if unused.

3. The voltage at a cmos gate input much not exceed the supply voltage.

4. Never insert or remove a cmos chip into or from the PCB or socket IC of your projects or learning lab unless the power switch is OFF.


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